Internal Talk, AMD, Internal
This internal AMD technical talk walks through GPU memory hierarchy, LDS/shared-memory banks, bank conflicts, padding, and XOR swizzling. It uses my IREE swizzle PR as a case study for how compiler-controlled shared-memory layout can reduce or reshape conflict pressure in attention kernels.
Talk, Sheraton Boston, MA, USA,
End-to-end deep neural networks’ (DNNs) training performance depends not only on the time spent in training the model weights but also on the time spent in loading and preprocessing the training data. Recent advances in GPU hardware have made training substantially faster. As a result, the bottleneck has shifted to the CPU-based input pipeline. This pipeline must fetch and transform each sample through multiple stages before it can be consumed by the GPU.
Graduate Seminar, Department of Computer Science and Automation, IISc, Bengaluru, India
This graduate seminar reviews fast convolution algorithms for neural networks, with an emphasis on Winograd minimal filtering and FFT-based convolution. It develops the forward and backward transformations and compares their arithmetic complexity with direct convolution.