Mitigating GPU Bank Conflicts with Swizzling
Date:
Internal technical talk at AMD, Internal
This internal AMD technical talk walks through GPU memory hierarchy, LDS/shared-memory banks, bank conflicts, padding, and XOR swizzling. It uses my IREE swizzle PR as a case study for how compiler-controlled shared-memory layout can reduce or reshape conflict pressure in attention kernels.
The talk builds from the hardware model to the compiler implementation, then uses MI300X evaluation data and instruction-level tracing to explain why the f16 and f32 results differ.